publication venue for
- Reliability-Aware Design Flow for Silicon Photonics On-Chip Interconnect 2014
- Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry 2012
- Reliability Modeling and Management of Nanophotonic On-Chip Networks 2012
- High-Throughput Layered LDPC Decoding Architecture 2009
- Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver 2005
- Accurate and efficient simulation of synchronous digital switching noise in systems on a chip 2005
- Interfacing synchronous and asynchronous modules within a high-speed pipeline 2000
- Clocked CMOS adiabatic logic with integrated single-phase power-clock supply 2000
- Synthesis of timed asynchronous circuits 1993